Compiler Scheduling for STA-Processors

Authors:
Gordon Cichon;P. Robelly;H. Seidel;M. Bronzel;Gerhard Fettweis
Affiliations:
Technische Universität, Dresden;Technische Universität, Dresden;Technische Universität, Dresden;Technische Universität, Dresden;Technische Universität, Dresden
Venue:
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
Year:
2004

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Abstract

This paper presents an adaptation of the list scheduling algorithm to generate code for processors of the Synchronous Transfer Architecture (STA) by applying techniques known from RISC and TTA. The proposed scheduling approach is based on informed, deterministic algorithms that can be implemented run-time efficiently. Although the presented compiler prototype does not generate optimized code, it provides a proof-of-concept of the feasibility of the proposed compiler architecture.