Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon

• Venue: ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
• Year: 2002

Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements bring in several challenges into the design of present day VLSI chips. In this paper we present the challenges faced and the approaches successfully adopted in the design of a complex 2.5 million gate high bandwidth data acquisition and processing VLSI chip (a trace-receiver chip, code-named Drishti) in a deep sub-micron technology at Texas Instruments India. The very high design complexity arises due to the rich architecture of the trace-receiver chip, the aggressive timing and performance requirements and its large size. The trace-receiver chip is highly configurable and scalable, thereby catering to both low-end systems, which are cost sensitive, and high-end applications, which demand performance. We present the innovative approaches that were applied to address the challenges encountered in meeting the aggressive design goals (which include functionality, timing, testability, manufacturability, reliability, system issues etc) and to bring the product early to market. Efficient logical and physical partitioning, design reuse and DFT strategies are a few of the techniques that were applied in this design. We present these along with details on the various analyses carried out as part of the design, including signal-integrity, reliability and system-level analyses, which were very critical in ensuring design-closure.