Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL

Authors:
M. Anouar Dziri;Firaz Samet;Flavio Rech Wagner;Wander O. Cesário;Ahmed A. Jerraya
Affiliations:
SLS Group, Grenoble, France;SLS Group, Grenoble, France;UFRGS, Porto Alegre, Brazil;SLS Group, Grenoble, France;SLS Group, Grenoble, France
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

Citing 11
Cited 2

Co-synthesis of hardware and software for digital embedded systems

Co-synthesis of hardware and software for digital embedded systems
Constructing application-specific heterogeneous embedded architectures from custom HW/SW applications

DAC '96 Proceedings of the 33rd annual Design Automation Conference
COSY communication IP's

Proceedings of the 37th Annual Design Automation Conference
Automatic generation and targeting of application specific operating systems and embedded systems software

Proceedings of the conference on Design, automation and test in Europe
A framework for object oriented hardware specification, verification, and synthesis

Proceedings of the 38th annual Design Automation Conference
Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Proceedings of the 38th annual Design Automation Conference
The standard SpecC language

Proceedings of the 14th international symposium on Systems synthesis
Component-based design approach for multicore SoCs

Proceedings of the 39th annual Design Automation Conference
Exploring Embedded-Systems Architectures with Artemis

Computer
Hardware-Software Cosynthesis for Microcontrollers

IEEE Design & Test
Zipper VDSL: a solution for robust duplex communication over telephone lines

IEEE Communications Magazine

System-level architectural exploration using allocation-on-demand technique

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Scheduling refinement in abstract RTOS models

ACM Transactions on Embedded Computing Systems (TECS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a full System-on-Chip (SoC) design flow from system specification to RT-level. A new approach to obtain a full path to implementation for SoC design is proposed. This approach combines architecture design space exploration using the VCC design environment and system synthesis using the ROSES design flow, allowing a true and complete system level design flow. The experiment with a VDSL application shows a significant reduction of design time.