Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The DLX Instruction Set Architecture Handbook
The DLX Instruction Set Architecture Handbook
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Superscalar Processor Validation at the Microarchitecture Level
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Lessons Learned in Data Reverse Engineering
WCRE '01 Proceedings of the Eighth Working Conference on Reverse Engineering (WCRE'01)
Automatic Test Program Generation: A Case Study
IEEE Design & Test
MicroGP—An Evolutionary Assembly Program Generator
Genetic Programming and Evolvable Machines
ACM SIGEVOlution
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In the design cycle of a microprocessor core, the unit is usually refined through a series of subsequent steps. To deliver a flaw free unit at the end of the process, in each stage a verification step is required. While it would be useful to automatically develop the set of test programs for verification concurrently to the design, in most of the existing approach verification is performed manually and starting from scratch. This paper presented a methodology for the automatic completion and refinement of existing verification programs. It shows a new technique for allowing a Genetic Programming-based framework to import an existing test-program set and assimilate it for further test generation. A case study is considered, in which a sample pipelined processor is used, and new test programs are generated starting from existing functional ones. Different metrics are targeted, and preliminary results are reported, showing the effectiveness of the method with respect to a pure random approach.