Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
VEEP A VEctor Editor and Preparer
DAC '82 Proceedings of the 19th Design Automation Conference
Functional Testing of Microprocessors
IEEE Transactions on Computers
Test Generation for Microprocessors
IEEE Transactions on Computers
An Abstract Model of Behavior for Hardware Descriptions
IEEE Transactions on Computers
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We have developed a method for fault simulation at the architectural level. This requires first an architectural level fault model. We have developed one based partially on the fault model proposed by Thatte and Abraham. An experiment with this fault model was done with a shift register described at both the architectural and gate levels. The resulting architectural level fault coverage tracked the gate level fault coverage obtained using the traditional stuck-at fault model. The next step was the development of an architectural level fault simulator, and an associated simulation model of the eight bit WE® 8000 microprocessor. The model was written in C, and 2512 faults were inserted in the model. A previously written test for the microprocessor was applied, and a fault coverage of 95% was obtained.