Multiple-Way Network Partitioning
IEEE Transactions on Computers
Exact evaluation of diagnostic test resolution
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Rapid diagnostic fault simulation of stuck-at faults in sequential circuits using compact lists
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fault simulation in a distributed environment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Diagnostic Fault Simulation of Sequential Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis
Proceedings of the conference on Design, automation and test in Europe - Volume 1
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This paper describes the parallelization of a diagnostic fault simulator for stuck-at faults in sequential circuits. The parallelization is performed by partitioning the diagnostic equivalence classes obtained by simulating the first few test vectors of the test set. The partitions are then simulated in parallel, independent of each other for the remaining vectors. Thus there is no communication overhead. Results on performance speedup and diagnostic resolution loss are provided for the ISCAS 89 benchmark circuits.