An approach to fast hierarchical fault simulation

  • Authors:
  • Akira Motohara;Motohide Murakami;Miki Urano;Yasuo Masuda;Masahide Sugano

  • Affiliations:
  • Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., Osaka, 570 Japan;Matsushita Soft Research Inc., Osaka, 570 Japan;Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., Osaka, 570 Japan;Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., Osaka, 570 Japan;Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., Osaka, 570 Japan

  • Venue:
  • DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
  • Year:
  • 1988

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Abstract

We present an approach to hierarchical fault simulation which generates several simulation-models of one circuit and carries out simulation for each. Fault insertion and simulation-model generation is done automatically. Switch-level simulation which utilizes look-up tables is as fast as gate-level simulation. Experimental results show that using behavioral description and switch-level truth tables is effective to improve simulation speed.