Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Introduction to VLSI Systems
A high level synthesis tool for MOS chip design
DAC '84 Proceedings of the 21st Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Fast, small, and static combinatorial CMOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A module area estimator for VLSI layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
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A comparison of the area and speed characteristics of CMOS PLA and Polycell representations of various control logic blocks was carried out. Both types of layout were generated automatically, and were derived from the same high level logic description. The major objectives were to quantify the differences between the two types of circuit and to predict Polycell speed and circuit area from the PLA truth table. Both objectives were achieved. Polycell layout was shown to be a viable alternative to PLAs under certain circumstances.