The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
ALPS: a generator of static CMOS layout from Boolean expressions
Proceedings of the fourth MIT conference on Advanced research in VLSI
ACORN: a local customization approach to DCVS physical design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Symbolic manipulation of Boolean functions using a graphical representation
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Comparison of CMOS PLA and polycell representations of control logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A retrospective on the Dorado, a high-performance personal computer
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
On synthesizing and identifying stuck-open testable CMOS combinational circuits (extended abstract)
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A structural representation for VLSI design
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Patchwork: layout from schematic annotations
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
| Hi-index | 0.00 |
We present ALPS, a new way to generate layout from Boolean equations. We use an original tree-structured representation of arbitrary Boolean expressions, more compact than classic disjunctive form, allowing fast symbolic manipulation and natural mapping onto silicon. This implementation of ALPS produces static CMOS layout using a cascode-switch style. We present measurements done on fabricated circuits. For a large class of functions, particularly semi-regular control logic, VLSI layout generated by ALPS compares favorably in speed and area to PLAS and Standard-Cell designs.