Design Automation for Digital Systems
Computer - IEEE Centennial: the state of computing
Programming in Prolog (2nd ed.)
Programming in Prolog (2nd ed.)
Digital logic testing and simulation
Digital logic testing and simulation
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Timing verification using HDTV
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
CLOVER: a timing constraints verification system
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
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Presents a novel approach for automating the timing design of interfaces between VLSI chips in microcomputer systems. The Prolog-based expert system, called TDS (for timing design system), incorporates the heuristic knowledge of the hardware designer. TDS is a rule-based system that interprets the specification sheets of VLSI chips and can synthesize, diagnose, and verify timing charts at the expert's level. The system uses a functional model based on timing specifications, not the structural information. TDS can model other interfaces that are based on timing specifications, such as standard bus interfaces.