Algorithms for accuracy enhancement in a hardware logic simulator

Authors:
P. Agrawal;R. Tutundjian;W. Dally
Affiliations:
AT&T Bell Laboratories, Murray Hill, NJ;AT&T Bell Laboratories, Murray Hill, NJ;Artificial Intelligence Laboratory, Massachusetts Institute of Technology, Cambridge, MA
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Abstract

In this paper, we describe a hardware multiple delay logic simulator that incorporates efficient timing analyses algorithms for event cancellations, spike and race analyses and oscillation detection. The algorithms are implemented on a set of reconfigurable processors, arranged in a pipelined configuration. Spike analysis is accomplished by dynamic pulse width measurement. Both zero and non-zero delay oscillations are detected. Results of simulating industrial VLSI chips are presented to illustrate the effectiveness of the algorithms with minimal performance penalty.