Simulation based verification of register-transfer level behavioral synthesis tools

Authors:
R. Ernst;S. Sutarwala;J. Y. Jou;M. Tong
Affiliations:
Technische Universitaet Braunschweig, Braunschweig, FRG;AT&T Bell Laboratories, Allentown, PA;AT&T Bell Laboratories, Murray Hill, NJ;AT&T Bell Laboratories, Murray Hill, NJ
Venue:
EURO-DAC '90 Proceedings of the conference on European design automation
Year:
1990

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Abstract

We present a simulation based system for verification of register-transfer level behavioral synthesis tools. Applications are tool debugging and automatic regression test. Key feature is a transformation of sequential circuits for application of pseudo-random test patterns. The results show a high relevance of verification with pseudo-random patterns.