Timing verification by formal signal interaction modeling in a multi-level timing simulator

Authors:
J. Benkoski;A. J. Strojwas
Affiliations:
SRC-CMU Research Center for CAD, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA;SRC-CMU Research Center for CAD, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Abstract

A new multi-level macromodeling technique for timing simulation has been developed. This technique is based upon the modeling of the behavior of subcircuits under single input changes. The possible interactions between multiple input changes determine the range of validity of the models. A formal method for developing the model validity conditions is presented. This work establishes a bridge between timing analysis by using single input change models, and timing simulation which correctly models signal interactions. The availability of a formal criterion for the validity of the models allows the dynamic identification of the parts of the circuit that require more accurate models. As a result, the cost advantage of high level models can be fully exploited while still allowing critical interactions to be simulated with high accuracy.