Graph algorithms and NP-completeness
Graph algorithms and NP-completeness
Introduction to VLSI Systems
A Decision Method for Temporal Logic Based on Resolution
Proceedings of the Fifth Conference on Foundations of Software Technology and Theoretical Computer Science
Dynamic Functional Testing for VLSI Circuits
IEEE Design & Test
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Temporal logic is proposed as a medium to describe the timing behaviour of digital systems. Queries on the timing properties of the digital systems can then be answered by testing the satisfiability of appropriately constructed temporal formulae. We suggest ways of improving the standard tableau method of testing the satisfiability of these formulae, and discuss results obtained from an implementation of this method. We claim that this can serve as a designers assistant to debug designs.