A note on clustering modules for floorplanning

Authors:
J. D. Gabbe;P. A. Subrahmanyam
Affiliations:
AT&T Bell Laboratories, Holmdel, NJ;AT&T Bell Laboratories, Holmdel, NJ
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

Citing 2
Cited 1

Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions

DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Clustering Algorithms

Clustering Algorithms

Nostradamus: a floorplanner of uncertain design

ISPD '98 Proceedings of the 1998 international symposium on Physical design

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Abstract

Many VLSI floorplanners work by recursively decomposing rectangular modules into lower-level rectangular modules until the leaf-level modules are reached[5]. Good layouts require good floorplans. The quality of a floorplan depends (among other things) on how the leaf-level modules are clustered into the various levels of the hierarchy. Some of the factors that determine the suitability of a decomposition are the geometry of the modules, the connectivity among modules, and timing constraints. Our experience with the mechanization of a VLSI design manager[1] has shown that the initial structural hierarchy that arises during synthesis from behavioral specifications is not always suitable for floorplanning. We describe hierarchical-clustering-based algorithms that lead to a small number of superior candidate hierarchies.