Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors
Microprocessors & Microsystems
Fast and efficient processor allocation algorithm for torus-based chip multiprocessors
Computers and Electrical Engineering
Energy characteristic of a processor allocator and a network-on-chip
International Journal of Applied Mathematics and Computer Science - SPECIAL SECTION: Efficient Resource Management for Grid-Enabled Applications
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Chip multiprocessors (CMPs) have become the primary approach to build high-performance microprocessors. Such systems require fast and efficient communication that can only be realized using Network on Chip (NoC), particularly for large systems. Allocation and management of on-chip processors are also important factors to achieve high efficiency. Designing processor allocator, job scheduler and NoC are major issues for future CMPs. In this paper we analyze architectures of NoC for CMPs. Such NoC parameters as topology, flow control and routing are studied and proposed for CMPs implementation. Modern processor allocation algorithms together with scheduling techniques are reviewed and suggested. Hardware structure of NoC-based CMPs is introduced for the recommended solutions. We propose hardware implementation of processor allocator and job scheduler, and place them together with on-chip processors on the same die.