Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors

Authors:
Dawid Zydek;Henry Selvaraj
Affiliations:
Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, NV, USA;Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, NV, USA
Venue:
Microprocessors & Microsystems
Year:
2010

Citing 9
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Energy characteristic of a processor allocator and a network-on-chip

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Abstract

Well-designed Processor Allocator (PA) is an important factor in modern Chip MultiProcessors (CMPs). It needs to be fast as well as area and energy efficient, because it is only a small component of the CMP. In this paper, we propose an architecture for such an efficient and fast PA. The PA structure is based on bit map approach and is driven by an Improved First Fit (IFF) algorithm, which is presented and described. Together with the proposed IFF technique, a new Improved Adaptive Scan (IAS) and an Improved Quick Allocation (IQA) algorithms are introduced and discussed and compared with previously known important techniques. The presented synthesis results reveal that the proposed PA achieves good frequency results while, at the same time is characterized by low logic utilization.