Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Extending Platform-Based Design to Network on Chip Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 6th FPGAworld Conference
| Hi-index | 0.00 |
Multi-core systems are getting bigger. The number of cores is doubling every 18 months, in corollary with the reformulated Moore's law. Soon, the number of cores that can be integrated together in a system will be so large, that it is appropriate to talk about a new SoC design paradigm, the Sea-of-Cores era. This development will not end, even when CMOS cannot be made any smaller. Instead, with the development of Through-Silicon Vias (TSVs), chips will be stacked in 3D, promising continuous scaling for a very long time ahead. As systems grow, programming and debugging of them will become harder. Methods for generating the systems from higher-level specifications will be necessary to manage design complexity. Also, there will be so many processors to be programmed, that the SW also will have to be automatically generated and distributed, much in the same way as a synthesis and place & route tool is doing today for HW. In this paper, we present a NoC generator that can generate an arbitrarily large Multi-core platform from an XML configuration file, targeted for single-chip FPGA platforms. The NoC generator also generates a device driver prototype together with a small test program that can be used as a template for creating larger programs.