Simulated annealing: theory and applications
Simulated annealing: theory and applications
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
A New Task Graph Model for Mapping Message Passing Applications
IEEE Transactions on Parallel and Distributed Systems
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parameter-optimized simulated annealing for application mapping on networks-on-chip
LION'12 Proceedings of the 6th international conference on Learning and Intelligent Optimization
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Simulated Annealing (SA) algorithm is a promising method for solving combinatorial optimization problems. The only limitation of applying the SA algorithm to application mapping problem on many-core networks-on-chip (NoCs) is its low speed. To alleviate this limitation, an accelerated SA algorithm called tk-SA algorithm is proposed in this work. The tk-SA algorithm starts the annealing process from a lower initial temperature tk with an optimized initial mapping solution. Based on the analysis of the typical behavior of the general SA algorithm, an efficient method is proposed for determining the temperature tk. Quantitative evaluations verify that the method is capable of obtaining an appropriate tk such that the tk-SA algorithm can reproduce the behavior of the full-range SA from temperature tk. Experimental results show that compared with a parameter-optimized SA algorithm, the proposed tk-SA algorithm achieves an average speedup of 1.55 without loss of solution quality.