CRAIS: a crossbar based adaptive interconnection scheme

Authors:
Chao Wang;Xi Li;Xuehai Zhou;Xiaojing Feng
Affiliations:
School of Computer Science, University of Science and Technology of China, China and Suzhou Institute of Advanced Study, University of Science and Technology of China, China;School of Computer Science, University of Science and Technology of China, China;School of Computer Science, University of Science and Technology of China, China;School of Computer Science, University of Science and Technology of China, China and Suzhou Institute of Advanced Study, University of Science and Technology of China, China
Venue:
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Year:
2012

Citing 3
Cited 0

Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Networks on Chips: A New SoC Paradigm

Computer
Multiprocessor System-on-Chip (MPSoC) Technology

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

This paper proposes a scheme of a crossbar based on-chip adaptive interconnection, named CRAIS. CRAIS utilizes crossbar to connect processors and IP cores in MPSoC. The interconnect topology of CRAIS can be dynamically reconfigured during execution. Empirical results on FPGA prototype demonstrated that CRAIS runs correctly with affordable hardware cost.