Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Optimal fully adaptive minimal wormhole routing for meshes
Journal of Parallel and Distributed Computing
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
A Framework for Designing Deadlock-Free Wormhole Routing Algorithms
IEEE Transactions on Parallel and Distributed Systems
Compressionless Routing: A Framework for Adaptive and Fault-Tolerant Routing
IEEE Transactions on Parallel and Distributed Systems
A Traffic-Balanced Adaptive Wormhole Routing Scheme for Two-Dimensional Meshes
IEEE Transactions on Computers
A Performance Model for Duato's Fully Adaptive Routing Algorithm in k$k$-Ary n$n$-Cubes
IEEE Transactions on Computers
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
GOAL: a load-balanced adaptive routing algorithm for torus networks
Proceedings of the 30th annual international symposium on Computer architecture
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Microprocessors & Microsystems
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Energy reduction through crosstalk avoidance coding in networks on chip
Journal of Systems Architecture: the EUROMICRO Journal
Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Designing Reliable and Efficient Networks on Chips
Designing Reliable and Efficient Networks on Chips
Hi-index | 0.00 |
Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual channels is important since it has a direct effect on the power consumption of NoCs. In this paper, we propose a novel systematic approach for designing deadlock-free routing algorithms for torus NoCs. Using this method a new deterministic routing algorithm (called TRANC) is proposed that uses only one virtual channel per physical channel in torus NoCs. We also propose an algorithmic mapping that enables extracting TRANC-based routing algorithms from existing routing algorithms, which can be both deterministic and adaptive. The simulation results show power consumption and performance improvements when using the proposed algorithms.