Designing Reliable and Efficient Networks on Chips

Authors:
Srinivasan Murali
Affiliations:
-
Venue:
Designing Reliable and Efficient Networks on Chips
Year:
2009

Citing 0
Cited 3

On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks

Microprocessors & Microsystems
Power-efficient deterministic and adaptive routing in torus networks-on-chip

Microprocessors & Microsystems
Efficient multicast schemes for 3-D Networks-on-Chip

Journal of Systems Architecture: the EUROMICRO Journal

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Abstract

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.