Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A comparative study of arbitration algorithms for the Alpha 21364 pipelined router
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
The Impact of Link Arbitration on Switch Performance
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
RoShaQ: High-performance on-chip router with shared queues
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
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On-chip interconnection networks simplify the integration of complex system-on-chips. The switches are the basic building blocks of such networks and their design critically affects the performance of the whole system. The transfer of data between the inputs and the outputs of the switch is performed by the crossbar, whose active connections are decided by the arbiter. In this paper, we design scalable dynamic-priority arbiters that are merged with the crossbar's multiplexers. The proposed RTL macros can adjust to various priority selection policies, while still following the same unified architecture. With this approach, sophisticated arbitration policies that yield significant network-throughput benefits can be implemented with negligible delay cost relative to the standard round-robin policy.