Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
System-level interconnect architecture exploration for custom memory organizations
Proceedings of the 14th international symposium on Systems synthesis
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
The BlackWidow High-Radix Clos Network
Proceedings of the 33rd annual international symposium on Computer Architecture
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
Proceedings of the 2006 international symposium on Low power electronics and design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Technology-Driven, Highly-Scalable Dragonfly Topology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration for optimizing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Many embedded computing platforms are highly specialised towards a given task and, consequently, sacrifice generality for high performance and energy efficiency at low cost. It is commonly accepted that integrating multiple processor cores on the same chip is the most promising way of delivering a high level of processing power under tight energy and cost constraints. Whereas the customisation of individual processing elements to particular tasks such as DSP or multimedia functions is a well-studied problem, the specialisation of applicationspecific on-chip and off-chip interconnects between processing elements has been largely neglected. In this paper we explore the design space of a tree-based network on chip of a synthesisable application-specific MPSoC. We empirically deduce the optimal network configurations, in terms of runtime and energy consumption, for a range of benchmark workloads. We present a machine learning approach that is able to predict optimal, or near-optimal, network-on-chip configurations for a new and as-yet-unseen workload. This new approach to automated NoC design yields designs that are, on average, within 9% of optimal design for the given workload. Moreover, the model predicts network configurations based on sample data from a single profiling run of the new application on a reference platform, providing the answer up to 280 times faster than an exhaustive search