Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
| Hi-index | 0.00 |
New trends and research outputs in VLSI fabrication technology have enabled integration over a billion transistors on a silicon die. To enable system development of this growing complexity, shared common bus structures were replaced by network on chip-based topologies such as 2D mesh, and torus. These systems used packet transfer techniques and provided communication mechanism among interconnected modules. These systems are realised as ASIC's or FPGA-based systems. Design of high performance systems requires an understanding of its internal characteristics, interaction among modules and working of these systems. These parameters are difficult to record on hardware platforms. To understand these process parameters, simulation studies are quite beneficial. This paper discusses the design and implementation of a simulator for network on chip-based systems. The topologies discussed are 2D mesh, torus and RiCoBiT: ring connected binary tree - a new structured and scalable topology for network on chip-based systems. The paper also studies the performance parameters of the same, along with some representative application and observations.