Throughput aware mapping for network on chip design of h.264 decoder

Authors:
Vu-Duc Ngo;Huy-Nam Nguyen;Younghwan Bae;Hanjin Cho;Hae-Wook Choi
Affiliations:
System VLSI Lab, SITI Research Center, School of Engineering, Information and Communications University (ICU), Yusong, Taejon, Korea;System VLSI Lab, SITI Research Center, School of Engineering, Information and Communications University (ICU), Yusong, Taejon, Korea;Basic Research Laboratory, ETRI, Daejeon, Korea;Basic Research Laboratory, ETRI, Daejeon, Korea;System VLSI Lab, SITI Research Center, School of Engineering, Information and Communications University (ICU), Yusong, Taejon, Korea
Venue:
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
Year:
2006

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Abstract

Network-on-Chip (NoC) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, we present the queuing theory based model for router to evaluate the performance of NoC in terms of drop probability, throughput and energy consumption. Then we apply the linear programming to optimize the allocation of the heterogeneously functional blocks (IPs) onto the given heterogeneous NoC architecture so as to obtain the maximum throughput as well as to optimize the energy dissipation of whole system. Finally, the three differently heterogenous Tree-based network topologies are proposed as the NoC architectures for the study case of H.264 Decoder. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic powers of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and energy consumptions.