Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Network Performance under Physical Constraints
ICPP '97 Proceedings of the international Conference on Parallel Processing
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the Conference on Design, Automation and Test in Europe
AdNoC case-study for Mpeg4 benchmark: improving performance and saving energy with an adaptive NoC
Proceedings of the 24th symposium on Integrated circuits and systems design
Throughput aware mapping for network on chip design of h.264 decoder
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
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The demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks has been introducing a new chip design paradigm so called on chip network. This paradigm promisingly offers a packet switched network among IPs to reduce the main problems in the very deep sub micron technologies that arise from non-scalable global wire delay, failure to achieve global synchronization, errors due to the signal integrity, non-scalable bus based functional interconnection, etc. This paper introduces interconnected or switched network topologies and also analyze their performances in terms of communication protocol related to the issues such as routing strategy, buffer size, routing algorithm , etc. The above mentioned evaluations are done by utilizing the tool that has been widely used in the research domain of computer network design, so called NS-2.