Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
How Can System-Level Design Solve the Interconnect Technology Scaling Problem?
Proceedings of the conference on Design, automation and test in Europe - Volume 1
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Communication latency aware low power NoC synthesis
Proceedings of the 43rd annual Design Automation Conference
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a new approach for system interconnect design exploration of application-specific multi-processor systems-on-chip (MPSoCs). As a novel contribution, we develop an analytical model for network-based communication design space exploration and generate fabric solutions with optimal cost-performance trade-offs, while considering various design constrains, such as power, area, and wirelength. For large systems, we also propose an efficient approach for obtaining competitive solutions with significant less computation time compared to the exhaustive approach. The accuracy of our analytical model is validated via SystemC simulation using several synthetic applications and an industrial SoC design.