Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
An overview of the Pentium Pro processor bus
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Pentium Pro processor workstation/server PCI Chipset
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Multiprocessor design verification for the PowerPC 620 microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Code generation and analysis for the functional verification of micro processors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An overview of the Pentium Pro processor bus
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
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The Pentium Pro microprocessor, the latest generation Intel Architecture processor, was designed to be used glue-lessly in multiprocessor (MP) systems. The processor and its associated chipset provide all the features that an MP system requires. Our challenge was to ensure that the Pentium Pro would be MP functional with the expected performance at first silicon. We accomplished this by developing a test methodology with self-checking test templates for validating the processor's MP features, and using micro-benchmarks and high-level system models to verify MP hardware scalability.