Effective TARO Pattern Generation

Authors:
Intaik Park;Ahmad Al-Yamani;Edward J. McCluskey
Affiliations:
Stanford University;Stanford University and LSI Logic Corporation;Stanford University
Venue:
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Year:
2005

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Abstract

TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to identify any ATPG tool that can generate TARO test patterns directly. This paper describes a technique to use an existing transition fault ATPG tool to efficiently generate TARO test patterns. This technique was used to generate TARO patterns for the ELF35 test chip. When these patterns were applied to the ELF 35 chips, all of the defective chips were discovered (no test escapes).