Multiple Fault Detection for Combinational Logic Circuits
IEEE Transactions on Computers
The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's
IEEE Transactions on Computers
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
Minimal Fault Tests for Redundant Combinational Networks
IEEE Transactions on Computers
A Practical Approach to Fault Detection in Combinational Networks
IEEE Transactions on Computers
On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy
IEEE Transactions on Computers
| Hi-index | 15.01 |
The problem of how to determine minimal sets of tests for single and multiple faults in irredundant combinational circuits is dealt with. It is shown that the "Equivalent Sum of Products" form of the given network contains all the information necessary to derive a min; mal test set. A simple procedure which generates a minimal test set Ts for single faults is described. Fault masking is then studied and it is shown how to find the multiple faults undetected by Ts. Finally a method which derives a nearly minimal multiple fault test set Tm where Ts [mi][/mi] Tm is given.