DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research

Authors:
Juergen Ributzka;Yuhei Hayashi;Fei Chen;Guang R. Gao
Affiliations:
University of Delaware, Newark, DE, USA;University of Delaware, Newark, DE, USA;ARM Inc., Austin, TX, USA;University of Delaware, Newark, DE, USA
Venue:
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Year:
2011

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Abstract

This paper introduces the Delaware Enhanced Emulation Platform (DEEP) - a FPGA-based emulation system for hardware/software co-verification of many-core chip architectures. This platform exhibits the following three characteristics: fast compilation of logic designs, debugging support, and affordability. It is based on a novel iterative emulation methodology for hardware design and verification. We also conducted a logic design and integration of a new architectural feature that provides Full/Empty bit fine-grain synchronization for the IBM Cyclops-64 many-core architecture and evaluated its performance against existing synchronization constructs.