Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Design and Implementation for High Speed LDPC Decoder with Layered Decoding
CMC '09 Proceedings of the 2009 WRI International Conference on Communications and Mobile Computing - Volume 01
Two-bit message passing decoders for LDPC codes over the binary symmetric channel
ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 3
Uniform all-integer quantization for irregular LDPC decoder
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
Flexible LDPC decoder design for multigigabit-per-second applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
FPGA Implementation of High Performance LDPC Decoder Using Modified 2-Bit Min-Sum Algorithm
ICCRD '10 Proceedings of the 2010 Second International Conference on Computer Research and Development
QSN: a simple circular-shift network for reconfigurable quasi-cyclic LDPC decoders
IEEE Transactions on Circuits and Systems II: Express Briefs
A min-sum iterative decoder based on pulsewidth message encoding
IEEE Transactions on Circuits and Systems II: Express Briefs
High-throughput layered LDPC decoding architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fully Parallel Stochastic LDPC Decoders
IEEE Transactions on Signal Processing
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Improved bit-flipping decoding of low-density parity-check codes
IEEE Transactions on Information Theory
Iterative decoder architectures
IEEE Communications Magazine
Computers and Electrical Engineering
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Hardware implementation of Low-Density Parity-Check (LDPC) decoders using conventional algorithms such as Sum-Product or Min-Sum requires large amount of hardware resources. A rather simplistic way to reduce hardware resources is to reduce the intrinsic message quantization. However this adversely affects the bit error rate (BER) performance significantly. In this paper, a resource efficient LDPC decoder based on a reduced complexity Min-Sum algorithm is presented. It reduces the inter-connect complexity by restricting the extrinsic message length to 2 bits and also simplifies the check node operation. Simulation at the algorithmic level shows that the proposed decoder achieves BER performance better than that of a 3-bit Min-Sum decoder, and therefore addresses the problem of massive BER performance degradation of a 2-bit Min-Sum decoder. The reduction in algorithmic complexity and further hardware optimization of the variable node leads to significant savings in hardware resources compared to 3-bit Min-Sum. An LDPC decoder with a code length of 1152 bits has been implemented on a Xilinx FPGA using the proposed algorithmic and hardware enhancements. With a 0.1dB BER performance gain to that of 3-bit Min-Sum decoder, the proposed decoder saves about 18% of FPGA slices and provides a higher throughput.