An area efficient LDPC decoder using a reduced complexity min-sum algorithm
Integration, the VLSI Journal
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In this paper, we present a uniform all-integer quantization for irregular LDPC decoder. The LLR values at the variable nodes and the check nodes are mapped to integer with their integer part of their value directly. Variable nodes are quantized to 6-bit integer and check nodes are quantized to 4-bit integer after the input channel messages are scaled up, and at a given iteration number the messages are scaled down. A lookup table is used to store the configuration parameters for quantization, and the hardware architecture of quantization is proposed. Simulations of (3048,7493) show the performance is better than the floating point in normalized min-sum and close to floating point in offset min-sum. The uniform all-integer quantization is easy to be implemented and does not require the floating point operations and so reduces the hardware complexity and lower power.