A relaxed half-stochastic iterative decoder for LDPC codes
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Stochastic decoding of LDPC codes over GF(q)
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
Majority-based tracking forecast memories for stochastic LDPC decoding
IEEE Transactions on Signal Processing
Relaxation dynamics in stochastic iterative decoders
IEEE Transactions on Signal Processing
A multimode shuffled iterative decoder architecture for high-rate RS-LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Stochastic decoding of turbo codes
IEEE Transactions on Signal Processing
Tracking Forecast Memories for Stochastic Decoding
Journal of Signal Processing Systems
An area efficient LDPC decoder using a reduced complexity min-sum algorithm
Integration, the VLSI Journal
Sequential logic to transform probabilities
Proceedings of the International Conference on Computer-Aided Design
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Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) decoders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-programmable gate-array (FPGA) device. The implemented decoder achieves a clock frequency of 222 MHz and a throughput of about 1.66 Gb/s at Eb/N0=4.25 dB (a bit error rate of 10-8). It provides decoding performance within 0.5 and 0.25 dB of the floating-point sum-product algorithm with 32 and 16 iterations, respectively, and similar error-floor behavior. The decoder uses less than 40% of the lookup tables, flip-flops, and IO ports available on the FPGA device. The results provided in this paper validate the potential of stochastic LDPC decoding as a practical and competitive fully parallel decoding approach.