Synthesizing interconnect-efficient low density parity check codes
Proceedings of the 41st annual Design Automation Conference
High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A scalable LDPC decoder ASIC architecture with bit-serial message exchange
Integration, the VLSI Journal
Optimal overlapped message passing decoding of quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices
IEEE Transactions on Communications
An area efficient LDPC decoder using a reduced complexity min-sum algorithm
Integration, the VLSI Journal
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Implementation constraints on iterative decoders applying message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the decoding algorithm. Turbo codes and low-density parity check codes, in particular, are evaluated in terms of their suitability for VLSI implementation in addition to their bit error rate performance as a function of signal-to-noise ratio. It is necessary to consider efficient realizations of iterative decoders when area, power, and throughput of the decoding implementation are constrained by practical design issues of communications receivers.