Synthesizing interconnect-efficient low density parity check codes

Authors:
Marghoob Mohiyuddin;Amit Prakash;Adnan Aziz;Wayne Wolf
Affiliations:
The University of Texas at Austin, Austin, TX;The University of Texas at Austin, Austin, TX;The University of Texas at Austin, Austin, TX;Princeton University, Princeton, NJ
Venue:
Proceedings of the 41st annual Design Automation Conference
Year:
2004

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Abstract

Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardware implementation of a Low Density Parity Check code (LDPC) indicates that interconnect complexity dominates the VLSI cost. We describe a heuristic interconnect-aware synthesis algorithm which generates LDPC codes that use an order of magnitude less wiring with little or no loss of coding efficiency.