A scalable LDPC decoder ASIC architecture with bit-serial message exchange
Integration, the VLSI Journal
A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
Design of high-throughput fully parallel LDPC decoders based on wire partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Iterative decoding of compound codes by probability propagation in graphical models
IEEE Journal on Selected Areas in Communications
An area efficient LDPC decoder using a reduced complexity min-sum algorithm
Integration, the VLSI Journal
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In this brief, we introduce a new iterative decoder implementation called pulsewidth-modulated min-sum (PWM-MS), in which messages are exchanged in a pulsewidth-encoded format. The advantages of this method are low switching activity, very low complexity check nodes, low routing congestion, and excellent energy efficiency. We implement a fully parallel PWM offset MS decoder for a (660, 484) regular (4, 15) low-density parity-check code with 4-bit quantization in 0.13-µm CMOS, with a core area of 5.76 mm2 (4.24-mm2 cell area or 556K equivalent AND gates). In postlayout simulations, this decoder achieves an average information throughput of 5.71 Gb/s and an energy consumption of 65.8 pJ per information bit at a signal-to-noise ratio of 5.5 dB. Our results show a 21% reduction in area, a 0.6-dB improvement in coding gain, and an energy efficiency improvement of 19% over the comparable bit-serial MS decoder architecture. We also demonstrate 3-bit implementations, in which the coding gain is traded off for further improvements in throughput, area, and energy efficiency.