Optimizing the Performance of Sparse Matrix-Vector Multiplication
Optimizing the Performance of Sparse Matrix-Vector Multiplication
How GPUs can outperform ASICs for fast LDPC decoding
Proceedings of the 23rd international conference on Supercomputing
Parallel LDPC decoding on GPUs using a stream-based computing approach
Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Low-density parity-check codes based on finite geometries: a rediscovery and new results
IEEE Transactions on Information Theory
Integration of GPU Computing in a Software Radio Environment
Journal of Signal Processing Systems
GPU-like on-chip system for decoding LDPC codes
ACM Transactions on Embedded Computing Systems (TECS)
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Software based decoding of low-density parity-check (LDPC) codes frequently takes very long time, thus the general purpose graphics processing units (GPGPUs) that support massively parallel processing can be very useful for speeding up the simulation. In LDPC decoding, the parity-check matrix H needs to be accessed at every node updating process, and the size of the matrix is often larger than that of GPU on-chip memory especially when the code length is long or the weight is high. In this work, the parity-check matrix of cyclic or quasi-cyclic (QC) LDPC codes is greatly compressed by exploiting the periodic property of the matrix. Also, vacant elements are eliminated from the sparse message arrays to utilize the coalesced access of global memory supported by GPGPUs. Regular projective geometry (PG) and irregular QC LDPC codes are used for sum-product algorithm based decoding with the GTX-285 NVIDIA graphics processing unit (GPU), and considerable speed-up results are obtained.