Architecture and Finite Precision Optimization for Layered LDPC Decoders
Journal of Signal Processing Systems
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In this paper, a new approximation of the check node rule algorithm is proposed for updating the check nodes messages in LDPC decoding. The new technique evaluates the check node min-sum magnitude algorithm using the Taylor series and results in reduced computational complexity and hardware implementation. The architecture of a check node processing unit, implementing the new alternative approximation of the check node, is also presented. The proposed method can achieve the same BER performance with a reduction of ~20% hardware complexity in the LDPE decoder. The simulation results obtained shows that the packet error rate performance of 10^-7 , which is the DVB-S2 requirement for MPEG packets transmitted, can be achieved with this new method.