Low complexity LDPC code decoders for next generation standards
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 13th international symposium on Low power electronics and design
Fast convergence algorithm for decoding of low density parity check codes
WSEAS TRANSACTIONS on COMMUNICATIONS
Techniques and architectures for hazard-free semi-parallel decoding of LDPC codes
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Conflict resolution by matrix reordering for DVB-T2 LDPC decoders
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
A multimode shuffled iterative decoder architecture for high-rate RS-LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
LDPC decoders with informed dynamic scheduling
IEEE Transactions on Communications
An energy efficient layered decoding architecture for LDPC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and Finite Precision Optimization for Layered LDPC Decoders
Journal of Signal Processing Systems
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The principle of "layered decoding" is extended to those codes not especially conceived for this practice, as to benefit of the increased convergence speed. Two different strategies are considered to solve the problem and the related architectures presented: one more straightforward, and based on the use for the soft output of the last value originated in a layer; the other based on the computation of the variation (or delta) of the soft output metrics to allow concurrent updates. Then, as in architecture-first approach, the performance are assessed for several widths of the layer, which remarks the robustness of the delta-mechanism to high parallelisation factors. As in the exact layered decoding, the average boost of two times in the convergence speed is shown.