Good Codes Based on Very Sparse Matrices
Proceedings of the 5th IMA Conference on Cryptography and Coding
Layered Decoding of Non-Layered LDPC Codes
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Approximate-min* constraint node updating for LDPC code decoding
MILCOM'03 Proceedings of the 2003 IEEE conference on Military communications - Volume I
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Serial Message-Passing Schedules for LDPC Decoding
IEEE Transactions on Information Theory
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The layered decoding algorithm has recently been proposed as an efficient means for the decoding of low-density parity-check (LDPC) codes, thanks to the remarkable improvement in the convergence speed (2×) of the decoding process. However, pipelined semi-parallel decoders suffer from violations or "hazards" between consecutive updates, which not only violate the layered principle but also enforce the loops in the code, thus spoiling the error correction performance. This paper describes three different techniques to properly reschedule the decoding updates, based on the careful insertion of "idle" cycles, to prevent the hazards of the pipeline mechanism. Also, different semi-parallel architectures of a layered LDPC decoder suitable for use with such techniques are analyzed. Then, taking the LDPC codes for the wireless local area network (IEEE 802.11n) as a case study, a detailed analysis of the performance attained with the proposed techniques and architectures is reported, and results of the logic synthesis on a 65nm low-power CMOS technology are shown.