LDPC decoder with an adaptive wordwidth datapath for energy and BER co-optimization

Authors:
Tinoosh Mohsenin;Houshmand Shirani-mehr;Bevan M. Baas
Affiliations:
CSEE Department, University of Maryland, Baltimore County, MD;ECE Department, University of California, Davis, MD;ECE Department, University of California, Davis, MD
Venue:
VLSI Design
Year:
2013

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Abstract

An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65nm CMOS. A 5.10mm2 low power decoder implementation achieves 85.7Gbps while operating at 185MHz and dissipates 16.4 pJ/bit at 1.3V with early termination. At 0.6V the decoder throughput is 9.3Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31mW. This is 4.6× lower than the state of the art reported power with an SNR loss of 0.35 dB at BER = 10-7.