Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels

Authors:
Weihuang Wang;Gwan Choi;Kiran K. Gunnam
Affiliations:
-;-;-
Venue:
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Year:
2009

Citing 0
Cited 4

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Dynamic power management for the iterative decoding of Turbo codes

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LDPC decoder with an adaptive wordwidth datapath for energy and BER co-optimization

VLSI Design

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Abstract

This paper presents a low-power LDPC decoder design for additive white Gaussian noise (AWGN) channels. The proposed decoding scheme provides constant-time decoding and thus facilitates real-time applications where guaranteed data rate is required. It analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The results are then used to dynamically adjust decoder frequency and switch between multiple-voltage levels; thereby energy use is minimized. It differs from recent publications on speculative LDPC decoding for block-fading channels. Our approach addresses the more difficult problem of decoding requirement prediction for data frames in AWGN channels. It is also directly applicable for fading channels. A decoder architecture utilizing offset min-sum layered decoding algorithm is presented. Up to 30% saving in decoding energy consumption is achieved with negligible coding performance degradation.