A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
SODA '03 Proceedings of the fourteenth annual ACM-SIAM symposium on Discrete algorithms
An Integrated Approach for Applying Dynamic Voltage Scaling to Hard Real-Time Systems
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
Workload prediction and dynamic voltage scaling for MPEG decoding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Speculative Energy Scheduling for LDPC Decoding
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Dynamic Power Management on LDPC Decoders
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Iterative decoding of binary block and convolutional codes
IEEE Transactions on Information Theory
Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)
IEEE Transactions on Information Theory
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Turbo codes are presently ubiquitous in the context of mobile wireless communications among other application domains. A decoder for such codes is typically the most power intensive component in the base-band processing chain of a wireless receiver. The iterative nature of these decoders represents a dynamic workload. This brief presents a dynamic power management policy for these decoders. An algorithm is proposed to tune a power manageable decoder according to a prediction of the workload involved within the decoding task. By reclaiming the timing slack left when operating the decoder at a high power mode, the proposed algorithm continuously looks for opportunities to switch to a lower power mode that guarantees the task completion. We apply this technique to an long term evolution Turbo decoder and explore the feasibility of a VLSI implementation on a CMOS technology of 65 nm. Energy savings of up to 54% were achieved with a relatively low loss in error-correction performance.