Routing Congestion in VLSI Circuits: Estimation and Optimization (Series on Integrated Circuits and Systems)
IEEE body area networks and medical implant communications
BodyNets '08 Proceedings of the ICST 3rd international conference on Body area networks
VLSI Circuits for Biomedical Applications
VLSI Circuits for Biomedical Applications
A Fast Encoding Method of QC-LDPC Code Used in ABS-S System
PACCS '09 Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems
Circuits and Systems for Future Generations of Wireless Communications
Circuits and Systems for Future Generations of Wireless Communications
An improved split-row threshold decoding algorithm for LDPC codes
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Quasicyclic low-density parity-check codes from circulant permutation matrices
IEEE Transactions on Information Theory
LDPC block and convolutional codes based on circulant matrices
IEEE Transactions on Information Theory
A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
Hi-index | 0.03 |
Over the last decade low density parity check (LDPC) codes have received significant attention due to their superior error correction performance, and have been adopted by recent communication standards such as 10 Gigabit Ethernet (10GBASE-T), digital video broadcasting (DVB-S2), WiMAX (802.16e), Wi-Fi (802.11n) and 60 GHz WPAN (802.15.3c). While there has been much research on LDPC decoders and their VLSI implementations, many diffculties to achieve requirements remain such as lower error floors, reduced interconnect complexities, smaller die areas, lower power dissipation, and design reconfigurability (run-time) to support multiple code lengths and code rates. This paper provides an overview of current research in LDPC decoder algorithms and architectures that are well suited for hardware implementations. Near and long-term trends of next generation LDPC requirements are made and an analysis of how current architectures will fare with the increasing demands on throughput, BER performance, power dissipation, and chip area (among others) that will be necessary for the widespread adoption of LDPC codecs in near-future applications.