A low-power VLSI architecture for turbo decoding
Proceedings of the 2003 international symposium on Low power electronics and design
VLSI architectures for SISO-APP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we propose a new design methodology targetedfor core-based designs using parameterized macro-cells(PMC's). This methodology provides the flexibility forinstance-based cores to be easily customized for applicationrequirements. By using few scaling parameters to characterizea PMC, a macrocell can be instantiated in virtually anysize depending on the required performance. Moreover, a newfirst-order macro delay model is proposed which is a functionof the scaling parameters of the PMC which enables accuratedelay predictions at the subsystem/core level. The proposeddelay model is suitable for use by a delay optimizer to determinethe optimum scaling parameters of individual PMC's ina core. A PMC library has been developed and used to designcores for communications applications. To demonstrate the effectivenessof the proposed methodology, several subsystemsused in a channel LDPC decoder were synthesized using thislibrary where the individual PMC's were optimized for minimumdelay. The resulting custom-quality layout have areasranging from 40 \times 100µm2 to 380 \times 200µm2 and delay in therange of 1:6ns to 10ns in 0:18µm, 1:8V CMOS technology.