A low power turbo/Viterbi decoder for 3GPP2 applications

Authors:
Chien-Ching Lin;Yen-Hsu Shih;Hsie-Chia Chang;Chen-Yi Lee
Affiliations:
Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.;Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.;Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.;Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Abstract

This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-µm standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.