Complexity issues in VLSI: optimal layouts for the shuffle-exchange graph and other networks
Complexity issues in VLSI: optimal layouts for the shuffle-exchange graph and other networks
Three dimensional circuit layouts
SIAM Journal on Computing
An approximation algorithm for Manhattan routing
Advances in computing research, vol. 2
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Channel routing of multiterminal nets
Journal of the ACM (JACM)
New algorithmic aspects of the Local Lemma with applications to routing and partitioning
Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms
Three-Dimensional VLSI: a case study
Journal of the ACM (JACM)
Node-Disjoint Paths on the Mesh and a New Trade-Off in VLSI Layout
SIAM Journal on Computing
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A polynomial time algorithm for optimal routing around a rectangle
SFCS '80 Proceedings of the 21st Annual Symposium on Foundations of Computer Science
Routing vertex disjoint steiner-trees in a cubic grid and connections to VLSI
Discrete Applied Mathematics
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Suppose that the terminals to be interconnected are situated in a rectangular area of length n and width w and the routing should be realized in a box of size w驴脳n驴脳h over this rectangle (single active layer routing) where w驴 = cw and n 驴 n驴 驴 n + 1. We prove that it is always possible with height h = O(n) and in time t = O(n) for a fixed w and both estimates are best possible (as far as the order of magnitude of n is concerned). The more theoretical case when the terminals are situated in two opposite parallel planes of the box (the 3-dimensional analogue of channel routing) is also studied.