Field-programmable gate arrays
Field-programmable gate arrays
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Quantified suboptimality of VLSI layout heuristics
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Measuring routing congestion for multi-layer global routing
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
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A global router with its consistent placer is proposed which aims to control wire-densities of channels. The routing order of nets and their routes are decided according to the channel which is predicted to have the maximum wire-density. The placer distributes the nets evenly with respect to the virtual length (half perimeter of the bounding box). Interesting features included are the interactive dynamic test to decide the form of predicting functions and the admissible region to consider the routing resources in placement stage. Experiments reveal some interesting phenomena that smaller maximum wire-density is attained in spite of comparable total wire-density and that smaller maximum wire-length in spite of larger total wire-length.